View AN2031_8730874.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/12 AN2031 application note 1 description the sta308a is a single chip solution for digital audio processing and control in multi-channel application. it provides output capabilities for ddx (direc t digital amplification). in conjunction with ddx power device, it provides high quality, high efficiency, all digital amplification. sta508 is a monolithic quad half bridge stage in multipower bcd technology. the device can be used as dual bridge or reconfi gured, by connecting config pin to v dd pin, as single bridge with double current capability. this device is particularly designed to make the output stage of a stereo ddx amplifier capa- ble to deliver 80 + 80w @thd = 10% at v cc = 35v output power on 8 ? load. in single btl configuration, is also capable to deliver a peak of 160w@thd = 10% at v cc = 35v on 4 ? load (t<= 1sec). 2 sta308-508// evaluati on board description in this board it is possible to solder sta308 or sta308a device how digital audio processor. there are three jumpers (jp2, jp3, jp6) to select the correct device. the board has one s/pdif input (electrical single ended and optical). in this board it is possible to use two different powers (10v to 35v on j2) and logic (5v on j1) stages or only one supply (10v to 35v on j2) for both stages. this feature is possible setting jp1 in ext-sel or int-sel respectively. u6 and u7 are configured to drive 3 or 2 ohm (over 250w) on the channel. 2.1 supply voltage, regulators the sta308-508// board uses 5v, 3.3v powe r regulation for logic circuitry and 10AN2031/0705 rev. 1
AN2031 application note 2/12 that have an adjustment range from +48db to -78db in 0.5db increments. in addition, the mat- er volume is adjustable from 0db to -127db in 0.5db steps. tone control registers boost or cut the tr eble and bass by +/-12db, in 2db steps. eq filters are iir biquads config urable by programmable coefficients. 2.4 power output the power level signals are applied to passive tw o-pole low pass filter, and provide low distor- tion audio power to the load. the output filter functions to prevent unwanted high frequency switching signals from reaching the load. filter designs for 2 ? . peak voltage on power pins must not exceed 35v. snubber networks are employed to protect the output mosfets from inductive transients, which can reach levels higher than the supply voltage. output snubber filter values are r18/c66 and r14/c53. the other critical components for device reliability are c47, c51, c58, c63 (1uf) and c48, c52, c59, c64 (100nf); these bypass capacitors from vcc and power gnd pins of sta508. these capacitors must be x7r ceramic or t antalum smd construction and must be located as close as possible to the device pins. the sta508 shuts down when it reaches 150c. 2.5 jumpers connector the sta308-508//-evb provides some jumpers to configure the board. 2.5.1 jumpers: jp1: (int-sel-ext): short on ext-sel to use different power supplies; short on int-sel to use only one power supply; jp2: (2.5a): short (with solder tin) if sta308 ic is solder on the board. if there is the sta308a this jumper could be opened; jp3: (2.5a): short (with solder tin) if sta308 ic is solder on the board. if there is the sta308a this jumper could be opened; jp4: short this jumper to use two different power supply; jp5: (optic- spdif -elec): short the central pin with elec pin to use electric s/pdif; short the central pin with optic pin to use the optical s/pdif. jp6: short (with solder tin) 3.3a and center if sta308a ic is solder on the board. if there is the sta308a this jumper could be short on 3.3v and center jp7: this pin must be open. 2.5.2 connectors: j1: logic supply (5v) j2: power supply (10v to 35v) j3: male 20 pin connector for plug control board j4: rca connector electric s/pdif j5: optical s/pdif sharp gp1f31r j6: connector for output load a
3/12 AN2031 application note 3 configure sta308a-508//- evb with lpt interface 1) plug the lpt interface on the board utilizing j3 of sta308a-508//-evb and j2 of lpt interface; 2) connect pc parallel port to t he lpt board using a parallel cable; 3) select s/pdif input mode (electric or optical) with jp5; 4) connect logic supply (+5v) on j1 and power supply [10v..35v] on j2; 5) connect output load on j6; 6) 6turn on the board; 7) run sta308a-508pcontro lpanel.exe on the pc. 3.1 configuring gui software: 1) go to "registers" page on gui. 2) click "autofind lpt" butto n. it appears the number of lpt port (0x278 or 0x378); 3) click "reset" button 4) click "power up" button 5) click "test board i/o". if "passed" it is ok. if "failed", then perform manual board-reset by press- ing sw1 button and try again. if still "failed" then make sure connections are ok. 6) go to "control" page on gui. 7) click "ext amp power up" to enable the output power. 8) increase "all" master volume control. 4 performances 4.1 thd+noise ratio versus output powe r at different input power supply input frequency: 1khz; output load: 4 ? ; blue: 15v; cyan: 20v; green: 25v; yellow: 30v; red: 35v; magenta: 37v figure 1. audio precision 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 10m 200 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 10m 200 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 w
AN2031 application note 4/12 4.2 thd+noise ratio versus output powe r at different input power supply input frequency: 1khz; output load: 2.67 ? ; blue: 15v; cyan: 20v; green: 25v; yellow: 30v; red: 35v; magenta: 37v figure 2. audio precision 4.3 thd+noise ratio versus output powe r at different input power supply input frequency: 1khz; output load: 2 ? ; blue: 15v; cyan: 20v; green: 25v; yellow: 30v; red: 35v; magenta: 37v figure 3. audio precision 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 10m 300 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 10m 300 20m 50m 100m 200m 500m 1 2 5 10 20 50 100 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 100m 300 200m 500m 1 2 5 10 20 50 100 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 100m 300 200m 500m 1 2 5 10 20 50 100 w
5/12 AN2031 application note 4.4 thd+noise ratio versus frequency at different output power input power supply: 25v; output load: 4 ? ; blue: 0db; cyan: -10db; green: -20db; figure 4. audio precision 5 schematic and layout 5.1 schematic figure 5. power section 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 1 0.02 0.05 0.1 0.2 0.5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 2a5 c6 100n 5v l5 fe rrite d1 sms160 3a3 vcc l2 lcl 1 3 2 j1 +5v 2 1 gnd logic + c3 330u 10v r1 10k l4 fe rrite + c8 10u 50v c14 100n + c2 100u 10v c7 100n + c4 10u 10v jp3 2v5 1 2 + c1 3 10u 10v r3 9.1k j2 +30v 1 2 pwr gnd jp2 2a5 1 2 c9 220n 50v jp1 5v sel 3 1 2 int ext sel u1 l4971d 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 c1 5 100n c16 100n vicino all'sta308 2v5 c12 22n u2 ld1086dt33 1 2 3 gnd ou t in c5 100n u3 ld1086dt25 1 2 3 gnd ou t in c10 100n c1 100n r2 2.7k l3 ferrite jp4 jumper 1 2 c1 1 2.2n r4 4.7k l6 fe rrite l1 220u 3v3
AN2031 application note 6/12 figure 6. connection section figure 7. s/p dif section tp2 test point er tp6 test point er r2 0 33 3v3 th _w tp7 test point er r5 10k 5v eapd sw1 button 1 3 pwdn sda tp5 test point er tp10 test point er 3v3 jp7 1 2 scl tp1 test point er j3 con 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 tp9 test point er tp4 test point er c1 7 1n tp3 test point er reset tp8 test point er d2 3v3 r7 330 lrcki spdif c2 4 100n c1 8 100n c2 0 100n c2 1 100n r6 560 5v bicki spdif non s aldare dat a spd if 3v3 r8 0 3a3 xti sp dif 3v3 3v3 u4 sta120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 c cd /f1 cc/f 0 cb /e2 ca/ e1 c0 /e0 vd+ dgn d rxp rxn fs yn c sck cs1 2/f ck ucbl sel m3 m2 mc k fi lt agnd va+ m0 m1 erf sda ta ce/ f2 verf r9 82 l7 fe rrite c2 2 15n r1 1 0 c1 9 100n r1 2 non s aldare j4 gp1f31r 3 2 1 dat a gnd +vs j5 rc a jack c2 3 470n jp 5 spdt/sm 3 1 2 elec opt - r1 0 non saldare
7/12 AN2031 application note figure 8. sta308a section 2v5 3v3 pwm2b 2v5 tp12 pwm1b c34 100n c33 100n 3v3 3v3 3v3 c41 100n pwdn 2v5 2v5 2v5 scl c35 100n c26 100n c29 100n bicki spdif jp6 jum per sold er 1 3 2 c38 100n 3a3 pwr pll pwr pll c30 100n sda 3v3 c40 100p reset 3v3 c25 100n c37 100n data spdif eapd nuovo c36 100n 2a5 xti spdif 3v3 c28 100n tp11 pwm1a u5 sta308 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 mvo te st_m ode vdd3 gnd vdd sdi_78 sdi_56 sdi_34 sdi_12 lrcki bi cki vdd3 gnd vdd reset pll_bypass sa sda scl xti filter_pll vdda gnda vdd3 ckout vdd gnd vdd3 out8b out8a out7b out7a out6b out6a vdd3 gnd vdd out5b out5a out4b out4a out3b out3a vdd3 gnd vdd out2b out2a out1b out1a eapd vdd3 gnd vdd bicko lrcko sdo_12 sdo _34 vdd3 gnd vdd sdo _56 sdo _78 pwdn c27 100n pwm2a lrcki spdif c32 100n c39 100n 3v3 c42 1n c31 100n r13 3.3k 2v5 2v5
AN2031 application note 8/12 figure 9. sta508 section figure 10. output filter section th _w pwm2b out1b_ ft500 pwm2a out1a c63 1u pwm2a c56 100n d4 1n4148 d3 1n4148 c50 100n th _w 500 out1a_ 3v3 u6 sta505 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd sub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a nc gndclean gndreg vdd vdd ibias config pwrdn tr ist ate fault th _w ar n in1a in1b in2a in2b vss vss vccsig vccsig r16 10k out1a_ tp13 3v3 out1b out1b 3v3 c49 100n vcc c52 100n pwm2b th _w 500 out1a c44 100n c54 100n c51 1u + c46 1000u 50v c43 100n tp 14 c64 100n eapd5 00 c58 1u eapd5 00 c60 100n c62 100n ft500 c55 100n c48 100n eapd u7 sta50 5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd sub out2b out2b vcc2b gnd2b gnd2a vcc2a out2a out2a out1b out1b vcc1b gnd1b gnd1a vcc1a out1a out1a nc gndclean gndreg vdd vdd ibias config pwrdn tristate fault th_w ar n in1a in1b in2a in2b vss vss vccsig vccsig + c57 1000u 50v c61 100n vcc r15 10k c47 1u out1b_ c59 100n c45 100n l8 22u c66 330p c68 100n c73 100n j6 con2 1 2 c69 1uf 63v c71 100n r18 20 ou t1a out1b_ r19 6.2 outa 505 outa 505 l11 22u out1a_ c65 100n l9 22u outb 505 r17 6.2 c53 330p r14 20 ou t1b c72 1n outb 505 c70 1nf 63v c67 1n l10 22u
9/12 AN2031 application note 5.2 layout figure 11. component layer figure 12. solder layer
AN2031 application note 10/12 figure 13. serigraphy
11/12 AN2031 application note table 1. revision history date revision description of changes july 2005 1 first issue
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners ? 2005 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com 12/12 AN2031 application note the present note which is for guidance onl y, aims at providing customers with information regarding their products in order for them to save time. as a result, stmicroelectr onics shall not be held liable for any direct, indirect or consequential damages with respect to any claims arising from the content of such a note and/or the use made by customers of the informat ion contained herein in connection with their products.

▲Up To Search▲

Price & Availability of AN2031

	To Download AN2031 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .